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Random-access memory
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#	Item
311	I’M ECC DRAM with integrated error correcting code A Revolutionary Product Family of Error-Correcting Memory for High Availability Applications Add to Reading List Source URL: www.storagesearch.com Language: English - Date: 2014-06-04 13:03:24 Computing Dynamic random-access memory DDR3 SDRAM ECC memory RAM parity Error detection and correction Random-access memory DDR SDRAM Memory rank Computer memory Computer hardware Digital media
312	HIERARCHICAL DIRECTORY CONTROLLERS IN THE NUMACHINE MULTIPROCESSOR by Alexander Grbic Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:44 Cache coherency CPU cache Cache Dynamic random-access memory Memory hierarchy Controller Bus sniffing Scalable Coherent Interface Computing Computer hardware Computer memory
313	AMULET3i An Asynchronous System-on-Chip Jim Garside HotChips 12 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:37:57 Computer architecture Computing Dynamic random-access memory AMULET microprocessor Integrated circuits Atmel AVR Intel Computer hardware Computer memory Microcontrollers
314	A Case for Intelligent DRAM: IRAM David Patterson, Tom Anderson, Kathy Yelick Computer Science Division University of California at Berkeley Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:47:37 CPU cache Alpha 21164 Dynamic random-access memory Memory controller The Berkeley IRAM Project PA-8000 Computer memory Computer hardware Computing
315	テクノロジーフォーラムD1 Add to Reading List Source URL: www.cies.tohoku.ac.jp Language: English - Date: 2015-03-04 03:00:55 Non-volatile memory Sankei Shimbun Aoba-ku Tohoku University Prefectures of Japan Technology Economy of Japan Spintronics Computer memory Magnetoresistive random access memory
316	Microsoft PowerPoint - present_isca02_2 Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-01-13 11:18:55 Dynamic random-access memory Computing Computer memory Prefetcher Windows XP
317	W9812G6JH 2M  4 BANKS  16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION .............................................................................................................. 3 Add to Reading List Source URL: www.netcheif.com Language: English - Date: 2014-11-19 14:57:51 Computing Dynamic random-access memory CAS latency Mobile DDR XDR DRAM Computer memory Computer hardware Synchronous dynamic random-access memory
318	Exploiting Memory Hierarchy Lecture 10 - Cache Memory ◆ SRAM: Add to Reading List Source URL: www.ee.ic.ac.uk Language: English - Date: 2001-11-27 12:22:51 CPU cache Cache Memory hierarchy Random-access memory Dynamic random-access memory Write buffer Bus sniffing Locality of reference Computer memory Computer hardware Computing
319	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu/flexram Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 11:50:27 Computer engineering Dynamic random-access memory CPU cache Random-access memory Processor-in-memory Cache Microarchitecture Memory hierarchy Computer memory Computer hardware Computing
320	Write-limited sorts and joins for persistent memory Stratis D. Viglas School of Informatics University of Edinburgh, UK [removed] Add to Reading List Source URL: www.vldb.org Language: English - Date: 2013-12-06 16:23:06 Theoretical computer science Analysis of algorithms External sorting Hash join Dynamic random-access memory Algorithm Merge sort Big O notation Mathematics Sorting algorithms Order theory

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